(1) Field of the Invention
The invention relates to the fabrication of integrated circuit devices, and more particularly, to a method of integrating different width spacers for the P and N areas into the double or more polysilicon process in the manufacture of integrated circuits.
(2) Description of the Prior Art
In the manufacture of integrated circuits, as device sizes are scaled down, the gate oxide and spacer layers become thinner. As a result, gate induced drain leakage (GIDL) becomes a significant problem. In their article, "Design for Suppression of Gate-Induced Drain Leakage in LDD MOSFET's Using a Quasi-Two-Dimensional Analytical Model," by Parke et al, IEEE Transactions on Electron Devices, Vol. 39, No. 7, July, 1992, pp. 1694-1702, the authors explain that the closer the N+ region is to the gate edge, the higher the vertical electrical field which enhances band-to-band tunneling in the device, hence causing gate induced drain leakage. The behaviors of N+ and P+ are different. Lateral diffusion of PMOS is much more significant than that of NMOS with the result that the P+ edge is much closer to the gate than is the N+ edge, when one spacer width is used for both NMOS and PMOS.
FIG. 1 illustrates a partially completed integrated circuit device formed on a semiconductor substrate 10. The N- and N+ regions are formed within the NMOS portion 12 and P- and P+ regions are formed within the PMOS portion 14 of the semiconductor substrate prior to the deposition of the interpoly oxide layer 25 in the conventional process of the prior art.
FIG. 2 shows a close-up view of the gate edge in the PMOS region. The sharp corner 9 of the gate easily creates a high electric field. FIG. 3 illustrates the drain current versus the drain voltage 31 for a pure junction. Line 33 shows the drain current versus the drain voltage for a junction such as 13 in FIG. 2 which is close to the sharp gate edge. Gate induced drain leakage 35 is observed for this junction.
U.S. Pat. No. 4,760,033 to Mueller teaches a process of using different N and P MOS spacer widths for reducing the under-diffusion of the implanted source-drain regions under the gate areas. U.S. Pat. No. 5,091,763 to Sanchez discloses the use of a conductive spacer coupled with a thin oxide spacer in order to form self-aligned source and drain regions.